1. Field of the Invention
Embodiments of the present invention relate to microelectronic device fabrication. In particular, an embodiment of the present invention relates to methods of fabricating bump limiting metallurgy (BLM) structure, which results in a dense intermetallic compound layer for increased bump strength and adhesion to metal pad and passivation layer.
2. State of the Art
The microelectronic device industry continues to see tremendous advances in technologies that permit increased circuit density and complexity, and equally dramatic decreases in power consumption and package sizes. Present semiconductor technology now permits single-chip microprocessors with many millions of transistors, operating at speeds of tens (or even hundreds) of MIPS (millions of instructions per second), to be packaged in relatively small, air-cooled microelectronic device packages. A result of such high density and high functionality in microelectronic devices has been the demand for increased numbers of external electrical connections to be present on the exterior of the microelectronic die in order to connect the microelectronic die to other components, such as an interposer.
The connection mechanism for such high density connection is generally wafer level bumping through a C4 (controlled collapse chip connection) process, because the size of the balls or bumps of the array can be made smaller to provide a higher density thereof, and thereby creating a greater number of connections from microelectronic die. A C4 is formed by placing an amount of solder on a microelectronic die pad and heating the solder above its melting point. The surface tension associated with the liquid solder causes the solder to form a solder ball. The solder ball retains its shape as it cools to form a solid solder ball or bump. While the description here is for wafer level bumping, the principle could be applied to ball grid array packaging.
As shown in FIG. 10, an exemplary microelectronic package 400 includes a microelectronic die 402 that is mounted on a substrate 404, such as an interposer, a motherboard, and the like, which functionally connects the microelectronic die 402 through a hierarchy of electrically conductive paths (not shown) to the other electronic components (not shown). The illustrated method for electronically mounting the microelectronic die 402 to the substrate 404 is called flip chip bonding. In this mounting method, electrically conductive Ball Limiting Metallurgy (BLM) 406 abutting a bond pad 424 on an active surface 410 of the microelectronic die 402 is attached directly to corresponding lands 412 on a surface 414 of the substrate 404 using solder bumps or balls 416, which are reflowed to from the attachment therebetween.
As shown in FIG. 11, the BLM 406 is connected through a passivation layer 422 to the bond pad 424. The passivation layer 422 comprises one or more layer of electrically insulative material, including, but not limited to, silicon dioxide, silicon nitride, and polyimide. The bond pad 424 is connected to a metal line 426 by way of a via 428. The via 428 and metal line 426 are disposed in at least one interlayer dielectric (illustrated as multiple layers 432a, 432b, and 432c).
The BLM 406 provides a reliable electrical and mechanical interface between the bond pad 424 and the solder bump 416. A typical BLM includes at least one conductive layer which will act to adhere to the solder ball 416 and bond pad 424 and to prevent contamination between the solder bump 416 and the microelectronic die 402. Of course, multiple layers may be used to form the BLM 406. For example, the BLM 406 may consist of an adhesion layer 442 for attachment to the bond pad 424, a barrier layer 444 over the adhesion layer 442 to prevent contamination between the solder bump 416 and microelectronic die (not shown), and a wetting layer 446 between the barrier layer 444 and the solder bump 416 to “wet” or adhere to the solder bump 416 material.
A nickel-vanadium-nitrogen alloy may be used as at least one layer in the BLM 406, particularly as an wetting layer 446. The solder bump 416 generally contains tin, such as lead/tin alloys or lead free solders, such as substantially pure tin or high tin content alloys (90% or more tin), such as tin/bismuth, eutectic tin/silver, ternary tin/silver/copper, eutectic tin/copper, and the like. However, solder bump 416 reflow attachment discussed above generally comprises a one-step reflow process. This one-step reflow process generates voids 138, shown in FIG. 4, in the wetting layer 446, specifically the nickel-vanadium-nitrogen alloy layer, due to high thermal budget of the reflow process. These voids 138 are formed during the formation of an intermetallic compound layer 440, which is the reaction product between the tin in the solder bump 416 and the nickel in the wetting layer 446. Intermetallic compounds form when two unlike metals diffuse into one another creating species materials which are combinations of the two materials. Intermetallic growth is the result of the diffusion of one material (i.e., the nickel of the nickel-vanadium-nitrogen alloy layer) into another (i.e., the solder bump 416) through crystal vacancies made available by defects, contamination, impurities, grain boundaries, and mechanical stress. If one material overwhelms the other in volume, as is the situation with the solder ball and the BLM, and diffusion occurs rapidly enough, crystal vacancies form. These vacancies attract each other which results in the creation of voids. These voids are called Kirkendall voids. Excessive Kirkendall voiding in the BLM lowers its adhesion and lowers device reliability. Furthermore, the one-step reflow process may also generate a solder bump 416 with low strength, which is primarily responsible for bump crack after reliability and chip attach yield loss due to non-optimized bump surface profile.
Therefore, it would be advantageous to develop apparatus and techniques to form an intermellatic compound layer which would have improved adhesion and device reliability.